A MOSFET is a variety of insulated gate field effect transistor (IGFET) wherein the insulated gate comprises a conductive material such as metal or relatively heavily doped polycrystalline silicon and the gate dielectric comprises an oxide such as silicon dioxide. When it is desired to fabricate a plurality of electrically isolated MOSFETs on a single chip, an insulating substrate is used in preference to a semiconductor substrate. The insulating material of such a substrate may be monocrystalline, as with sapphire, beryllia or spinel, or may be amorphous, as with quartz (glass). When an amorphous insulating substrate such as quartz is used, the MOSFETs on the surface thereof are fabricated in appropriately doped islands of polycrystalline silicon and will hereinafter be referred to as poly-on-glass devices. When the MOSFETs are disposed on the surface of a monocrystalline insulating substrate, they are typically fabricated in appropriately doped monocrystalline silicon islands. Such MOSFETs are hereinafter referred to as SOS (silicon-on-sapphire) devices although it should be understood that substrates of beryllia or spinel should exhibit similar characteristics in the context of the subject invention.
In the fabrication of poly-on-glass and SOS devices, following the deposition and definition of one or more silicon islands on the substrate surface, a gate oxide is formed so as to selectively overlie a portion or portions of the silicon island(s). A conductive gate electrode, typically of doped polycrystalline silicon, is then formed over the gate oxide so as to be capacitively coupled with a portion of the underlying silicon island. A high quality device requires a high quality insulated gate which in turn requires a high quality silicon dioxide dielectric. However, despite a variety of modifications suggested in conventional fabrication processes, non-uniform gate dielectric strength remains a problem.
Examples of conventional approaches to improving gate dielectric strength may be found in U.S. Pat. No. 3,974,515, IGFET ON INSULATING SUBSTRATE, A. C. Ipri et al., Aug. 10, 1976; U.S. Pat. No. 4,341,569, SEMICONDUCTOR ON INSULATOR LASER PROCESS, G. Yaron et al., July 27, 1982; U.S. Pat. No. 4,368,085, SOS ISLAND EDGE PASSIVATION STRUCTURE, J. L. Peel, Jan. 11, 1983; and U.S. Pat. No. 4,242,156, METHOD OF FABRICATING AN SOS ISLAND EDGE PASSIVATION STRUCTURE, J. L. Peel, Dec. 30, 1980. In an effort to overcome the gate dielectric strength problems that remain despite the suggestions of the prior art, the method of the present invention was conceived.